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ADT7475
Product Description
The ADT7475 is a complete thermal monitor and multiple
fan controller for any system requiring thermal monitoring
and cooling. The device communicates with the system via
a serial system management bus. The serial bus controller
has a serial data line for reading and writing addresses and
data (Pin 16), and an input line for the serial clock (Pin 1).
All control and programming functions for the ADT7475
are performed over the serial bus. In addition, a pin can be
reconfigured as an SMBALERT output to signal
out-of-limit conditions.
Quick Comparison Between ADT7473 and ADT7475
? The ADT7473 supports advanced dynamic T MIN
features while the ADT7475 does not.
? Acoustic smoothing is improved on the ADT7475.
? THERM can be selected as an output only on the
ADT7475.
? The ADT7475 has two additional configuration
registers.
? The ADT7475 has other minor register changes.
The ADT7475 is similar to the ADT7473 in that it is
powered by a supply no greater than 3.6 V. Exceeding this
specification results in irreversible damage to the ADT7475.
Signal pins (TACH/PWM) should be pulled up or clamped
to 3.6 V maximum. See the Specifications Section for more
information.
Recommended Implementation
Configuring the ADT7475 as shown in Figure 12 allows
the system designer to use the following features:
? Two PWM outputs for fan control of up-to-three fans
(the front and rear chassis fans are connected in
parallel).
? Three TACH fan speed measurement inputs
? V CC measured internally through Pin 3.
? CPU temperature measured using the Remote 1
temperature channel.
? Ambient temperature measured through the Remote 2
temperature channel.
? Bidirectional THERM pin. This feature allows
Intel ? Pentium ? 4 PROCHOT monitoring and can
function as an overtemperature THERM output. The
THERM pin can alternatively be programmed as an
SMBALERT system interrupt output.
FRONT
CHASSIS
FAN
ADT7475
PWM1
TACH2
TACH1
CPU FAN
REAR
CHASSIS
FAN
PWM3
TACH3
D2+
D2 ?
THERM
PROCHOT
CPU
AMBIENT
TEMPERATURE
D1+
D1 ?
SDA
SCL
SMBALERT
GND
ICH
Figure 12. ADT7475 Configuration
Serial Bus Interface
On PCs and servers, control of the ADT7475 is carried out
using the SMBus. The ADT7475 is connected to this bus as
a slave device under the control of a master controller, which
is usually (but not necessarily) the ICH.
The ADT7475 has a fixed 7-bit serial bus address of
0101110 or 0x2E. The read/write bit must be added to get the
8-bit address (01011100 or 0x5C). Data is sent over the serial
bus in sequences of nine clock pulses, that is, eight bits of
data followed by an acknowledge bit from the slave device.
Transitions on the data line must occur during the low period
of the clock signal and remain stable during the high period
because a low-to-high transition when the clock is high may
be interpreted as a stop signal. The number of data bytes that
can be transmitted over the serial bus in a single read or write
operation is limited only by what the master and slave
devices can handle.
When all data bytes are read or written, stop conditions are
established. In write mode, the master pulls the data line high
during the tenth clock pulse to assert a stop condition.
In read mode, the master device overrides the acknowledge
bit by pulling the data line high during the low period before
the ninth clock pulse; this is known as no acknowledge. The
master takes the data line low during the low period before
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